RSS BotBM to Lobste.rsEnglish · 2 months ago

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

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cross-posted to:
riscv@lemmy.ml

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Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

RSS BotBM to Lobste.rsEnglish · 2 months ago

0

cross-posted to:
riscv@lemmy.ml

Alibaba's XuanTie C950 chip hits 30 tokens/second, with a 1.9-second first-token latency, on Qwen-3.8 27B - no emulation layer required.

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